LA-F541P Boardview & Schematic

A B C D E DAM00 VinDafixe.colml/Compal Confidential MODEL NAME : DAM01 1 PCB NO : LA-F541P BOM P/N : Schematic Document 1 Berlinetta MLK CFL-H (Coffee Lake-H) 2 2018-01-10 3 Rev: DVT2.0 4 2 A &$ ,& !"# $ $ % && ' ! ( !"# && ' ! ( *" # $ $ % && ' *( *" # && ' *( 3 *" # - -. / && ' *( 0& 1 1 ! )! * +* # &$ # &$ $ ,$ $ #& * 2 $2 ( #& 3 $ $ 4 ! + )! Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL P01-Cover Page Rev AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.1(X00) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F541P Date: Friday, March 23, 2018 Sheet 1 o f 76 B C D E A B C D E 256M*32 x4 =8Gb ,128-bit Memory GDDR5, VRAM * 4 8Gbit GDDR5 memory P.28~30 Memory Bus (DDR4) DDRIV-DIMM X2 CPU XDP GPU GB4C-128 Vinafix.com Intel Dual Channel 1.2V DDR4 2666 MHz P.14~15 Conn. Coffee Lake-H GTX N17P-G0 40W/4GB P.6 Processor 1 GTX N17P-G1 MaxQ 35W/4GB 45W 6C+2 32GB Max (4G, 8G,16G) 1 Quadro PEG 3.0 x16 lane 42 x 28mm DDI x 1 port 3 DP to HDMI Converter HDMI HDMI 2.0/HDCP2.2 BGA 1440 Balls Parade PS175 B2 P.39 LSPCon Conn. N18P-Q1 30W/4GB 4096x2160 60Hz P.40 P.7~13 N18P-Q3 30W MaxQ /4GB DMI x4 P.23~27 100MHz UHD 3840x2160@60Hz 8GB/s DDI x 2 port1,2 Intel Alpine Ridge TBT USB3.1 Type C (TBT) (4K*2K, eDP 1.4a, PSR2) SP C-stepping Conn. eDP *4 lane PCI-E Gen3 x 4 P.34 PCH Port 17,18,19,20 P.35~36 (Gen 2 10Gbps) P.38 M.2 Slot A Key-E PCI-E Gen2 x 1 Port 1 SATA3.0 Port 1B HDD Conn. TI PD PCI-E x4 TPS65982DC (WLAN+BT5.0) P.44 P.42 P.37 USB2.0 Port 4 2 Port 1A M.2 Slot C Key-M 2 3 in 1 Socket for UHS-II Card Reader SD4.0 PCI-E Gen2 x 1 Port 2 (SATA/PCIe SSD) SD/SDHC/SD3.0/SD 4.0 RTS5242-GR P.43 P.50 P.50 Intel USB 3.1 Gen 1 (5Gbps) CNL-H-PCH USB 3.1 Gen1 Port 1 USB 3.1 Gen1 Re-Driver Type A Conn. 24 x 25mm PS8713 P.46 USB 3.1 Gen 1 (5Gbps) ( USB Charger ) Type A Conn. P.47 USB 3.1 Gen1 Port 2 BGA 837 Balls ( USB Charger ) 3 USB Powershare Port 2 USB2.0 CM246 USB2.0 Port 1 USB Powershare P.47 USB2.0 Port 9 TPS2546 TPS2546 Touch Panel I2C Bus Port 0 P.45 P.45 Conn. P.34 Touch Panel RGB Camera Port 12 USB2.0 Conn. P.34 720P HD P.34 USB2.0 Port 7 Finger Print (Wacom G12+ Controller) Conn. (leveraged with Berlinetta MLK) contact USB 2.0 FFC P.48 SPI Flash SPI (in Power Button leveraged with (LaFerrari) ) (BIOS 32MB) HD Audio x9 Common P.17 Audio Codec ARD Headphone / Mic. Jack ALC3266 P.52 ( Combo ) P.53 3 FFS LNG2DMTR SMBus DMIC P.44 connect to Audio Board P16~22 PCH AMP TAS5768M GPU sequence chip TPM 2.0 SPI eSPI Bus SLG4U41821VTR Power On/Off CKT. NPCT750JAAYX 33MHz Int. Speaker x2 Digital MIC Conn. P.41 x9 Common code P.41 MEC 5105 Rev:C DC/DC Interface CKT. KB Board P.31~33 P.48 DC-IN Conn. PWM PS/2 BCBUS KBC KSIO Int.KBD 4 P.54 I2C ECE1117 Fan Control 4 Touch Pad P.40 P.40 HZH-1-TR C Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL P02-Block Diagram Rev AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.1(X00) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F541P Date: Friday, March 23, 2018 Sheet 2 o f 76 A B C D E A B C D E 1 Compal Confidential 2 3 Project Code : DAM00 / DAM01 File Name : Vinafix.com 1 LA-F541P MB LS-E331P Audio Board 2 JAUDIO BtB Conn. JKB Finger Print JTP 8 pin 15 pin FFC 8 pin FFC FFC Touch Pad LS-E332P KB controller Board JLED 3 4 pin FFC Front Side LED/B 4 4 Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL P03-Daughter/B block diagram Rev AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.1(X00) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Friday, March 23, 2018 Sheet 3 o f 76 A B C D E A Board ID Resistor USB3.1 DESTINATION USB 2.0 DESTINATION USB OC# DESTINATION X00 240K 1 USB Conn 1 (Right Side) 0 USB Conn 1 (Right Side) X01 130K 1 USB Conn 1 (Right Side) 2 USB Conn 2 (Left Side) 1 USB Conn 2 (Left Side) X02 3 None 2 X03 2 VinaUfiSxB.Ccoonnm2 (Left Side) 4 NGFF-1 WLAN + BT 3 A00 5 None 4 3 None 6 None 5 7 Finger Print 6 4 None 8 None 7 9 Touch Screen 5 None 10 None 11 None 6 None 12 RGB CAMERA PCI EXPRESS DESTINATION USB3.0 DESTINATION Lane 1 NGFF-1 WLAN + BT 7 None Lane 2 None 8 None Lane 3 None 9 None Lane 4 None 10 None Lane 5 CARD READER Lane 6 None CLKOUT_PCIE DESTINATION CLKOUT_PCIE DESTINATION Lane 7 None 0 None 10 None Lane 8 None 1 None 11 None 1 Lane 9 SSD 2 None 12 None 1 Lane 10 SSD SATA DESTINATION 3 NGFF-1 WLAN 13 None Lane 11 SSD 0A N/A 4 CARD READER 14 None Lane 12 SSD 1A SSD 5 Thunderbolt 15 None Lane 13 None 0B N/A 6 NGFF-2 SSD Lane 14 None 1B N/A 7 GPU Lane 15 None 2 HDD 8 None Lane 16 None 3 N/A 9 None Lane 17 4 N/A Lane 18 5 N/A Lane 19 Alpine Ridge Lane 20 The 30 HSIO lanes on PCH-H supports the following configurations: 1. Up to 24 PCIe* Lanes DDI DESTINATION LPC DESTINATION -- A maximum of 16 PCIe* Ports (or devices) can be enabled 1 Alpine Ridge ESPI/LPC0 MEC5105 When a GbE Port is enabled, the maximum number of PCIe* Ports (or devices) that can be enabled reduces based off the following: 2 Alpine Ridge LPC1 DEBUG PORT Max PCIe* Ports (or devices) = 16 - GbE (0 or 1) -- PCIe* Lanes 1-4 (PCIe* Controller #1), 5-8 (PCIe* Controller #2), 9-12 (PCIe* 3 HDMI 2.0 Controller #3), 13-16 (PCIe* Controller #4), 17-20 (PCIe* Controller #5), and 21-24 (PCIe* Controller #6) can be individually configured 2. Up to 6 SATA Lanes -- A maximum of 6 SATA Ports (or devices) can be enabled -- SATA Lane 0 has the flexibility to be mapped to Flex I/O Lane 16 or 18 -- SATA Lane 1 has the flexibility to be mapped to Flex I/O Lane 17 or 19 3. Up to 10 USB 3.1 Lanes -- A maximum of 10 USB 3.1 Ports (or devices) can be enabled 4. Up to 4 GbE Lanes -- A maximum of 1 GbE Port (or device) can be enabled 5. Supports up to 3 Remapped (IntelR Rapid Storage Technology) PCIe* storage devices -- x2 and x4 PCIe* NVMe SSD -- x2 IntelR Optane? Memory Device -- See the " PC I Express * (PCIe*) " chapt er f or t he P CH PCI e* Controllers,configurations , and lanes that can be used for IntelR Rapid Storage Technology PCIe* storage support 6. For unused SATA/PCIe* Combo Lanes, Flex I/O Lanes that can be configured as PCIe* or SATA, the lanes must be statically assigned to SATA or PCIe* via the SATA/PCIe Combo Port Soft Straps discussed in the SPI Programming Guide and through the IntelR Flash Image Tool (FIT) tool. Symbol Note : Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date Deciphered Date : means Digital Ground 2017/06/21 2027/06/21 Title : means Analog Ground THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL P04-Notes List AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 0.1(X00) LA-F541P 76 Date: Friday, March 23, 2018 Sheet 4 of A 5 4 3 2 1 SMBUS Address [0x9a] 1K 1K AW44 1K +3V_PCH +3VS BB43 +3VS 1K SMBCLK Vinafix.com DMN65D8 PCH_SMBCLK DIMMA SMBDATA PCH_SMBDATA DMN65D8 D 5.1K QH4 D +3VS DIMMB 5.1K PCH AR38 I2C0_SCK 4.7K I2C0_SCK_TS Touch Screen AT42 I2C0_SDA 4.7K I2C0_SDA_TS FFS +3VS_TP 2.4K +3VS_TP XDP 2.4K TP DMN65D8 I2C1_SCK_TP_C AR41 I2C1_SCK_TP DMN65D8 I2C1_SDA_TP_C AR44 I2C1_SDA_TP QE2 AW45 AW42 SML1_SMBCLK 1K C SML1_SMBDAT 1K +3V_PCH Connect PCH SMB03 C 2.2K E11 D8 2.2K +3VALW_5105 N10 PBAT_SMBCLK 100 ohm 100 ohm A12 PBAT_SMBDAT BATT 0x16 PBAT DATA/CLK SMB06 10K M3 CHARGER_SMBCLK +3VALW_5105 0 ohm CHARGER_SCL CHARGER 0x12 Power Charger SMB10 CHARGER_SMBDAT 0 ohm CHARGER_SDA MEC5105 N2 10K 2.2KK 2.2K +3VALW_5105 M3 UPD_SMBCLK UPD_SMBCLK_R B N2 PD Controller PD SMB04 B UPD_SMBDAT UPD_SMBDAT_R 2.2KK 1.8K 2.2K +3VALW_5105 DGPU_PEX_RST# 1.8K +3VALW_5105 B6 GPU_SMBCLK DMN65D8 GPU F7 GPU_SMBDAT DMN65D8 0x9E GPU SMB05 QV21 E7 AUDIO_AMP_SMBCLK +3VS I2C0_SCK_DSP I2C0_SDA_DSP D7 DMN65D8 Codec DMN65D8 AUDIO_AMP_SMBDAT QE18 Audio + AMP SMB00 AMP 2.2K +3VALW_5105 A 2.2K A E10 CLK_TP_SIO Touch PAD Touch Pad SMB02 C12 DAT_TP_SIO Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL P05-SMBus block diagram Rev AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.1(X00) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Friday, March 23, 2018 Sheet 5 o f 76 5 4 3 2 1 5 4 3 2 1 +1V_PCH JTAG +1V_PCH RH492 1 2 XDP_PLTRST# 1 XDP@ 2.2K_0402_5% +3V_PCH CH3 RH474 1 XDP@ 2 1K_0402_5% CFG3 XDP_TDO RH493 1 Vinafix.com 0.1U_0402_25V6 RH540 1 @ 2 0_0402_1% CPU_XDP_TDO <9> D 2 PCH_SYS_PWROK_XDP 2 +1V_PCH RH475 1 @ 2 0_0402_5% +1V_PCH CPU_XDP_TDI <9> 2.2K_0402_5% <9,22> XDP_PREQ# JXDP 2 CFG17 <9> XDP_TDI RH541 1 @ 2 0_0402_1% CPU_XDP_TMS <9> D <9,22> XDP_PRDY# 1 GND1 4 CFG16 <9> XDP_TMS RH542 1 @ 2 0_0402_1% CPU_XDP_TRST# <9,22> 3 GND0 OBSFN_C0 6 XDP_TRST# RH543 1 @ 2 0_0402_1% +VCCST <9> CFG0 5 OBSFN_A0 OBSFN_C1 8 - <9> CFG1 7 OBSFN_A1 GND3 10 PCH_SPI_WP# <17> CFG0 9 GND2 OBSDATA_C0 12 CFG8 <9> 11 OBSDATA_A0 OBSDATA_C1 14 CFG9 <9> 13 OBSDATA_A1 GND5 16 RH97 1 @ 2 100_0402_5% PCH_JTAG_TDO <9> CFG2 CFG3 15 GND4 OBSDATA_C2 18 CFG10 <9> RH98 1 @ 2 51_0402_5% PCH_JTAG_TMS <9> CFG3 17 OBSDATA_A2 OBSDATA_C3 20 CFG11 <9> RH100 1 @ 2 51_0402_5% PCH_JTAG_TDI 19 OBSDATA_A3 GND7 22 <9> XDP_BPM#0 21 GND6 OBSFN_D0 24 CFG19 <9> <9> XDP_BPM#1 23 OBSFN_B0 OBSFN_D1 26 CFG18 <9> 25 OBSFN_B1 GND9 28 +VCCSTG <9> CFG4 27 GND8 OBSDATA_D0 30 CFG12 <9> <9> CFG5 29 OBSDATA_B0 OBSDATA_D1 32 CFG13 <9> 31 OBSDATA_B1 GND11 34 <9> CFG6 33 GND10 OBSDATA_D2 36 CFG14 <9> <9> CFG7 35 OBSDATA_B2 OBSDATA_D3 38 CFG15 <9> 37 OBSDATA_B3 GND13 40 RH494 1 2 51_0402_5% CPU_XDP_TMS A00_0303: Del PWRBTN#_XDP XDP_PWRGOOD 39 GND12 ITPCLK/HOOK4 42 PCH_XDP_CLK_P <17> RH495 1 2 51_0402_5% CPU_XDP_TDI 41 PWRGOOD/HOOK0 ITPCLK#/HOOK5 44 PCH_XDP_CLK_N <17> RH496 1 2 51_0402_5% CPU_XDP_TDO TC287 @ 43 HOOK1 VCC_OBS_CD 46 PWR_DEBUG#_XDP 45 VCC_OBS_AB RESET#/HOOK6 48 XDP_PLTRST# PCH_SYS_PWROK_XDP 47 HOOK2 DBR#/HOOK7 50 XDP_DBRESET# 49 HOOK3 GND15 52 <14,15,18,44> PCH_SMBDATA PCH_JTAG_TCK 51 GND14 XDP_TDO <14,15,18,44> PCH_SMBCLK CPU_XDP_TCK 53 SDA TD0 54 XDP_TRST# 55 SCL TRST# 56 XDP_TDI RH95 1 @ 2 100_0402_5% PCH_JTAG_TCK <18> PCH_JTAG_TCK 2 0_0402_1% 57 TCK1 XDP_TMS <9> CPUR_HX4D9P1_TC1K @ 59 TCK0 TDI 58 PCH_SPI_WP#_XDP RH573 2 51_0402_5% CPU_XDP_TCK <18> PCH_JTAGX TMS 60 1 XDP@ 2 1K_0402_5% GND16 GND17 RH498 1 RH497 1 @ 2 51_0402_5% CPU_XDP_TRST# SAMTE_BSH-030-01-L-D-A CONN@ C XDP_TMS RH12 1 @ 2 0_0402_1% PCH_JTAG_TMS C PCH_JTAG_TMS <18> XDP_TDI RH477 1 @ 2 0_0402_1% PCH_JTAG_TDI PCH_JTAG_TDI <18> XDP_PWRGOOD XDP_TDO RH478 1 @ 2 0_0402_1% PCH_JTAG_TDO 1 <18> PCH_ITP_PMODE RH479 1 XDP@ 2 0_0402_5% 2 PCH_JTAG_TDO <18> <9,16> PLTRST_CPU# RH480 1@ 2 1K_0402_5% XDP_PLTRST# CD3328 <17> PCH_SPI_SI PCH_SYS_PWROK_XDP .1U_0402_16V7K <18,48> SYS_PWROK RH489 1 XDP@ 2 1K_0402_5% RH490 1 @ 2 0_0402_5% <18,48> PCH_RSMRST#_EC RH481 1 XDP@ 2 1K_0402_5% <9,33> H_VCCST_PWRGD RH482 1 @ 2 1K_0402_5% XDP_PWRGOOD +3VS +3V_PCH_DSW +VCCIO 1 1 1 A00_0303: Del PWRBTN#_XDP @ RH5 A00_0312: Pop RH2 & RH6 for PCH PWRBTN control 3K_0402_5% RH483 RH2 150_0402_5% 1K_0201_5% 2 2 2 PWR_DEBUG#_XDP RH488 1 XDP@ 2 1K_0402_5% CFG0 RH6 1 2 0_0402_5% XDP_DBRESET# RH8 1 @ 2 0_0402_1% SYS_RESET# <18,51> SIO_PWRBTN# <18,48> B CH174 XDP@ B 0.1U_0402_25V6 CH175 1 1 0.1U_0402_25V6 XDP@ 2 2 A A Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL P06-XDP CONN Rev AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.1(X00) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Friday, March 23, 2018 Sheet 6 o f 76 5 4 3 2 1 5 4 3 2 1 D CFL-H C <23> PEG_HTX_C_GRX_P[0..15] PEG_HTX_C_GRX_P[0..15] PEG_GTX_C_HRX_P15 UH1C B25 PEG_HTX_GRX_P15 DIS@ CH5 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P15 <23> PEG_HTX_C_GRX_N[0..15] PEG_HTX_C_GRX_N[0..15] PEG_GTX_C_HRX_N15 E25 PEG_TXP_0 A25 PEG_HTX_GRX_N15 DIS@ CH6 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N15 <23> PEG_GTX_C_HRX_P[0..15] PEG_GTX_C_HRX_P[0..15] D25 PEG_RXP_0 PEG_TXN_0 <23> PEG_GTX_C_HRX_N[0..15] PEG_GTX_C_HRX_N[0..15] PEG_GTX_C_HRX_P14 PEG_HTX_GRX_P14 DIS@ CH7 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P14 PEG_GTX_C_HRX_N14 PEG_RXN_0 B24 PEG_HTX_GRX_N14 DIS@ CH8 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N14 PEG_TXP_1 C24 PEG_GTX_C_HRX_P13 E24 PEG_TXN_1 PEG_HTX_GRX_P13 DIS@ CH9 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P13 PEG_GTX_C_HRX_N13 F24 PEG_RXP_1 PEG_HTX_GRX_N13 DIS@ CH10 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N13 B23 Vinafix.com PEG_GTX_C_HRX_P12 PEG_RXN_1 PEG_TXP_2 A23 PEG_HTX_GRX_P12 DIS@ CH11 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P12 PEG_GTX_C_HRX_N12 PEG_TXN_2 PEG_HTX_GRX_N12 DIS@ CH12 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N12 E23 D23 PEG_RXP_2 B22 PEG_TXP_3 C22 PEG_RXN_2 PEG_TXN_3 E22 F22 PEG_RXP_3 PEG_RXN_3 PEG_GTX_C_HRX_P11 E21 B21 PEG_HTX_GRX_P11 DIS@ CH13 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P11 D PEG_GTX_C_HRX_N11 D21 PEG_RXP_4 PEG_TXP_4 A21 PEG_HTX_GRX_N11 DIS@ CH14 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N11 PEG_RXN_4 PEG_TXN_4 PEG_GTX_C_HRX_P10 E20 B20 PEG_HTX_GRX_P10 DIS@ CH15 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P10 PEG_GTX_C_HRX_N10 F20 PEG_RXP_5 PEG_TXP_5 C20 PEG_HTX_GRX_N10 DIS@ CH16 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N10 PEG_TXN_5 PEG_RXN_5 PEG_GTX_C_HRX_P9 E19 B19 PEG_HTX_GRX_P9 DIS@ CH17 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P9 PEG_GTX_C_HRX_N9 D19 PEG_RXP_6 PEG_TXP_6 A19 PEG_HTX_GRX_N9 DIS@ CH18 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N9 PEG_TXN_6 PEG_RXN_6 PEG_GTX_C_HRX_P8 E18 B18 PEG_HTX_GRX_P8 DIS@ CH19 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P8 PEG_GTX_C_HRX_N8 F18 PEG_RXP_7 PEG_TXP_7 C18 PEG_HTX_GRX_N8 DIS@ CH20 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N8 PEG_TXN_7 PEG_RXN_7 PEG_GTX_C_HRX_P7 D17 A17 PEG_HTX_GRX_P7 DIS@ CH21 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P7 PEG_GTX_C_HRX_N7 E17 PEG_RXP_8 PEG_TXP_8 B17 PEG_HTX_GRX_N7 DIS@ CH22 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N7 PEG_TXN_8 PEG_RXN_8 PEG_GTX_C_HRX_P6 F16 C16 PEG_HTX_GRX_P6 DIS@ CH23 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P6 PEG_GTX_C_HRX_N6 E16 PEG_RXP_9 PEG_TXP_9 B16 PEG_HTX_GRX_N6 DIS@ CH24 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N6 PEG_TXN_9 PEG_RXN_9 PEG_GTX_C_HRX_P5 D15 A15 PEG_HTX_GRX_P5 DIS@ CH25 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P5 PEG_GTX_C_HRX_N5 E15 PEG_RXP_10 PEG_TXP_10 B15 PEG_HTX_GRX_N5 DIS@ CH26 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N5 PEG_TXN_10 PEG_RXN_10 PEG_GTX_C_HRX_P4 F14 C14 PEG_HTX_GRX_P4 DIS@ CH27 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P4 PEG_GTX_C_HRX_N4 E14 PEG_RXP_11 PEG_TXP_11 B14 PEG_HTX_GRX_N4 DIS@ CH28 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N4 PEG_TXN_11 PEG_RXN_11 PEG_GTX_C_HRX_P3 D13 A13 PEG_HTX_GRX_P3 DIS@ CH29 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P3 PEG_GTX_C_HRX_N3 E13 PEG_RXP_12 PEG_TXP_12 B13 PEG_HTX_GRX_N3 DIS@ CH30 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N3 PEG_TXN_12 PEG_RXN_12 PEG_GTX_C_HRX_P2 F12 C12 PEG_HTX_GRX_P2 DIS@ CH31 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P2 PEG_GTX_C_HRX_N2 E12 PEG_RXP_13 PEG_TXP_13 B12 PEG_HTX_GRX_N2 DIS@ CH32 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N2 PEG_TXN_13 PEG_RXN_13 PEG_GTX_C_HRX_P1 D11 A11 PEG_HTX_GRX_P1 DIS@ CH33 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P1 PEG_GTX_C_HRX_N1 E11 PEG_RXP_14 PEG_TXP_14 B11 PEG_HTX_GRX_N1 DIS@ CH34 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N1 PEG_TXN_14 PEG_RXN_14 +VCCIO PEG_GTX_C_HRX_P0 F10 C10 PEG_HTX_GRX_P0 DIS@ CH35 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_P0 PEG_GTX_C_HRX_N0 E10 PEG_RXP_15 PEG_TXP_15 B10 PEG_HTX_GRX_N0 DIS@ CH36 1 2 0.22U_0201_6.3V6M PEG_HTX_C_GRX_N0 PEG_TXN_15 PEG_RXN_15 RH24 1 2 24.9_0201_1% PEG_RCOMP G2 PEG_RCOMP C Trace Width/Space: 15 mil/ 15 mil Max Trace Length: 600 mil <19> DMI_CRX_PTX_P0 D8 B8 DMI_CTX_PRX_P0 <19> <19> DMI_CRX_PTX_N0 E8 DMI_RXP_0 DMI_TXP_0 A8 DMI_CTX_PRX_N0 <19> DMI_TXN_0 <19> DMI_CRX_PTX_P1 DMI_RXN_0 DMI_CTX_PRX_P1 <19> <19> DMI_CRX_PTX_N1 DMI_CTX_PRX_N1 <19> E6 C6 <19> DMI_CRX_PTX_P2 F6 DMI_RXP_1 DMI_TXP_1 B6 DMI_CTX_PRX_P2 <19> <19> DMI_CRX_PTX_N2 DMI_TXN_1 DMI_CTX_PRX_N2 <19> DMI_RXN_1 <19> DMI_CRX_PTX_P3 DMI_CTX_PRX_P3 <19> <19> DMI_CRX_PTX_N3 D5 B5 DMI_CTX_PRX_N3 <19> E5 DMI_RXP_2 DMI_TXP_2 A5 DMI_TXN_2 DMI_RXN_2 J8 D4 J9 DMI_RXP_3 3 OF 13 DMI_TXP_3 B4 DMI_RXN_3 DMI_TXN_3 CFL-H_BGA1440 @ CFL-H UH1D B <35> CPU_DP1_P0 K36 D29 EDP_TXP0 <34> B <35> CPU_DP1_N0 K37 DDI1_TXP_0 EDP_TXP_0 E29 EDP_TXN0 <34> To Alpine Ridge <35> CPU_DP1_P1 J35 DDI1_TXN_0 EDP_TXN_0 F28 EDP_TXP1 <34> <35> CPU_DP1_N1 J34 DDI1_TXP_1 EDP_TXP_1 E28 EDP_TXN1 <34> <35> CPU_DP1_P2 H37 DDI1_TXN_1 EDP_TXN_1 A29 EDP_TXP2 <34> <35> CPU_DP1_N2 H36 DDI1_TXP_2 EDP_TXP_2 B29 EDP_TXN2 <34> <35> CPU_DP1_P3 J37 DDI1_TXN_2 EDP_TXN_2 C28 EDP_TXP3 <34> <35> CPU_DP1_N3 J38 DDI1_TXP_3 EDP_TXP_3 B28 EDP_TXN3 <34> EDP_TXN_3 DDI1_TXN_3 <35> CPU_DP1_AUXP D27 C26 EDP_AUXP <34> <35> CPU_DP1_AUXN E27 DDI1_AUXP EDP_AUXP B26 EDP_AUXN <34> EDP_AUXN DDI1_AUXN <35> CPU_DP2_P0 H34 A33 EDP_DISP_UTIL RH456 1 @ 2 0_0402_5% BIA_PWM_PCH +VCCIO <35> CPU_DP2_N0 H33 DDI2_TXP_0 EDP_DISP_UTIL EDP_COMP <16,34> <35> CPU_DP2_P1 F37 DDI2_TXN_0 To Alpine Ridge <35> CPU_DP2_N1 G38 DDI2_TXP_1 D37 RH30 1 2 24.9_0402_1% <35> CPU_DP2_P2 F34 DDI2_TXN_1 DISP_RCOMP <35> CPU_DP2_N2 F35 DDI2_TXP_2 EDP_COMP <35> CPU_DP2_P3 E37 DDI2_TXN_2 CAD Note:Trace width=20 mils ,Spacing=25mil, <35> CPU_DP2_N3 E36 DDI2_TXP_3 Max length=100 mils. DDI2_TXN_3 <35> CPU_DP2_AUXP F26 <35> CPU_DP2_AUXN E26 DDI2_AUXP DDI2_AUXN <39> CPU_DP3_P0 C34 <39> CPU_DP3_N0 D34 DDI3_TXP_0 <39> CPU_DP3_P1 B36 DDI3_TXN_0 <39> CPU_DP3_N1 B34 DDI3_TXP_1 <39> CPU_DP3_P2 F33 DDI3_TXN_1 <39> CPU_DP3_N2 E33 DDI3_TXP_2 To DP to HDMI Converter <39> CPU_DP3_P3 C33 DDI3_TXN_2 4 (UM1/PS175B2) <39> CPU_DP3_N3 B33 DDI3_TXP_3 DDI3_TXN_3 G27 AUD_AZA_CPU_SCLK <18> PROC_AUDIO_CLK G25 2 20_0402A_U5D%_AZA_CPU_ASUDDO_AZA_<C1P8>U_SDI_R <39> CPU_DP3_AUXP A27 PROC_AUDIO_SDI G29 <39> CPU_DP3_AUXN B27 DDI3_AUXP AUD_AZA_CPU_SDI RH145 1 <18> DDI3_AUXN 4 ofP1R3 OC_AUDIO_SDO CFL-H_BGA1440 A @ A Security Classification Compal Secret Data Compal Electronics, Inc. Issued Date 2017/06/21 Deciphered Date 2027/06/21 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL P07-CPU(1/7) DMI,PEG,DDI,EDP AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C 0.1(X00) Date: Friday, March 23, 2018 Sheet 7 o f 76 5 4 3 2 1 5 4 3 2 1 Interleave CFL-H UH1A CFL-H UH1B DDR CHANNEL A DDR CHANNEL B DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4 DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4 DDR_A_D0 BR6 AG1 M_CLK_DDR0 <14> DDR_B_D0 BT11 AM9 M_CLK_DDR2 <15> DDR_A_D1 BT6 DDR0_DQ_0/DDR0_DQ_0 DDR0_CKP_0/DDR0_CKP_0 AG2 M_CLK_DDR#0 <14> DDR_B_D1 BR11 DDR1_DQ_0/DDR0_DQ_16 DDR1_CKP_0/DDR1_CKP_0 AN9 M_CLK_DDR#2 <15> DDR_A_D2 BP3 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 AK2 M_CLK_DDR1 DDR_B_D6 DDR1_DQ_1/DDR0_DQ_17 DDR1_CKN_0/DDR1_CKN_0 AM7 M_CLK_DDR3 <14> DDR_A_D[0..63] DDR_A_D7 BR3 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_1/DDR0_CKP_1 AK1 M_CLK_DDR#1 <14> DDR_B_D2 BT9 DDR1_DQ_2/DDR0_DQ_18 DDR1_CKP_1/DDR1_CKP_1 AM8 M_CLK_DDR#3 <15> <14> DDR_A_MA[0..13] DDR_A_D4 BN5 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 AL3 <14> DDR_B_D4 BR8 DDR1_DQ_3/DDR0_DQ_19 DDR1_CKN_1/DDR1_CKN_1 AM11 <15> <14> DDR_A_DQS#[0..7] DDR_A_D5 DDR_B_D5 BP11 DDR1_DQ_4/DDR0_DQ_20 AM10 <14> DDR_A_DQS[0..7] DDR_A_D6 Vinafix.com BP6 DDR0_DQ_4/DDR0_DQ_4 NC/DDR0_CKP_2 AK3 DDR_B_D3 BN11 DDR1_DQ_5/DDR0_DQ_21 NC/DDR1_CKP_2 AJ10 DDR_A_D3 NC/DDR0_CKN_2 AL2 DDR_B_D7 BP8 DDR1_DQ_6/DDR0_DQ_22 NC/DDR1_CKN_2 AJ11 BP2 DDR0_DQ_5/DDR0_DQ_5 NC/DDR0_CKP_3 AL1 BN8 NC/DDR1_CKP_3 BN3 DDR0_DQ_6/DDR0_DQ_6 DDR_A_D9 BL4 DDR0_DQ_7/DDR0_DQ_7 NC/DDR0_CKN_3 DDR_B_D12 BL12 DDR1_DQ_7/DDR0_DQ_23 NC/DDR1_CKN_3 D DDR_A_D13 BL5 DDR0_DQ_8/DDR0_DQ_8 AT1 DDR_CKE0_DIMMA <14> DDR_B_D8 BL11 DDR1_DQ_8/DDR0_DQ_24 AT8 DDR_CKE2_DIMMB <15> D DDR_A_D10 BL2 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_0/DDR0_CKE_0 AT2 DDR_CKE1_DIMMA <14> DDR_B_D9 BL8 DDR1_DQ_9/DDR0_DQ_25 DDR1_CKE_0/DDR1_CKE_0 AT10 DDR_CKE3_DIMMB <15> DDR_A_D11 BM1 DDR0_DQ_10/DDR0_DQ_10 DDR0_CKE_1/DDR0_CKE_1 AT3 DDR_B_D10 BJ8 DDR1_DQ_10/DDR0_DQ_26 DDR1_CKE_1/DDR1_CKE_1 AT7 <15> DDR_B_D[0..63] DDR_A_D12 BK4 DDR0_DQ_11/DDR0_DQ_11 DDR0_CKE_2/DDR0_CKE_2 AT5 <15> DDR_B_MA[0..13] DDR_A_D8 BK5 DDR0_DQ_12/DDR0_DQ_12 DDR0_CKE_3/DDR0_CKE_3 DDR_B_D14 BJ11 DDR1_DQ_11/DDR0_DQ_27 DDR1_CKE_2/DDR1_CKE_2 AT11 <15> DDR_B_DQS#[0..7] DDR_A_D14 BK1 DDR0_DQ_13/DDR0_DQ_13 <15> DDR_B_DQS[0..7] DDR_A_D15 BK2 DDR0_DQ_14/DDR0_DQ_14 AD5 DDR_B_D11 BJ10 DDR1_DQ_12/DDR0_DQ_28 DDR1_CKE_3/DDR1_CKE_3 DDR_A_D20 BG4 DDR0_DQ_15/DDR0_DQ_15 DDR0_CS#_0/DDR0_CS#_0 AE2 DDR0_CS#_1/DDR0_CS#_1 AD2 DDR_CS0_DIMMA# <14> DDR_B_D13 BL7 DDR1_DQ_13/DDR0_DQ_29 AF11 DDR_CS2_DIMMB# <15> DDR_CS1_DIMMA# <14> DDR_B_D15 BJ7 DDR1_DQ_14/DDR0_DQ_30 DDR1_CS#_0/DDR1_CS#_0 AE7 DDR_CS3_DIMMB# <15> DDR_B_D16 BG11 DDR1_DQ_15/DDR0_DQ_31 DDR1_CS#_1/DDR1_CS#_1 AF10 DDR_A_D16 BG5 DDR0_DQ_16/DDR0_DQ_32 NC/DDR0_CS#_2 AE5 DDR_B_D17 BG10 DDR1_DQ_16/DDR0_DQ_48 NC/DDR1_CS#_2 AE10 DDR_A_D23 BF4 DDR0_DQ_17/DDR0_DQ_33 NC/DDR0_CS#_3 DDR_B_D21 BG8 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_CS#_3 DDR_A_D19 BF5 DDR0_DQ_18/DDR0_DQ_34 AD3 M_ODT0 <14> DDR_B_D19 BF8 DDR1_DQ_18/DDR0_DQ_50 AF7 M_ODT2 <15> DDR_A_D21 BG2 DDR0_DQ_19/DDR0_DQ_35 DDR0_ODT_0/DDR0_ODT_0 AE4 M_ODT1 <14> DDR_B_D18 BF11 DDR1_DQ_19/DDR0_DQ_51 DDR1_ODT_0/DDR1_ODT_0 AE8 M_ODT3 <15> DDR_A_D17 BG1 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_ODT_1 AE1 DDR_B_D22 BF10 DDR1_DQ_20/DDR0_DQ_52 NC/DDR1_ODT_1 AE9 DDR_A_D22 BF1 DDR0_DQ_21/DDR0_DQ_37 NC/DDR0_ODT_2 AD4 DDR_B_D20 BG7 DDR1_DQ_21/DDR0_DQ_53 NC/DDR1_ODT_2 AE11 DDR_A_D18 BF2 DDR0_DQ_22/DDR0_DQ_38 NC/DDR0_ODT_3 DDR_B_D23 BF7 DDR1_DQ_22/DDR0_DQ_54 NC/DDR1_ODT_3 DDR_A_D24 BD2 DDR0_DQ_23/DDR0_DQ_39 AH5 DDR_A_BS0 <14> DDR_B_D26 BB11 DDR1_DQ_23/DDR0_DQ_55 DDR1_CAB_3/DDR1_MA_16 AH10 DDR_B_RAS# <15> DDR_A_D25 BD1 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAB_4/DDR0_BA_0 AH1 DDR_A_BS1 <14> DDR_B_D24 BC11 DDR1_DQ_24/DDR0_DQ_56 DDR1_CAB_2/DDR1_MA_14 AH11 DDR_B_WE# <15> DDR_A_D26 BC4 DDR0_DQ_25/