MacBook A2338 (820-01814) Boardview & Schematic
Interactive boardview and full 131-page schematic for the MacBook A2338 (820-01814) logic board. Search a designator or a net name and the viewer will show you exactly where the part sits, which side it is on, and what every pad connects to.
6,773Components
3,946Nets
23,610Pads
1,457Test points
334.54 × 121.26 mmBoard size
131Schematic pages
Interactive boardview
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Top side Bottom side Through-hole Test point
Schematic
The full 131-page schematic for this board. Use your browser's zoom and find controls inside the viewer — it is a real PDF, so the text is selectable and searchable. If it does not render below, the download button at the top opens it directly.
MacBook A2338 (820-01814) — 131-page schematic
Open in new tabDownload PDFAbout this MacBook A2338 (820-01814) board
This page is generated from the board file itself, so the map above is the manufacturer layout rather than a redrawing of it. The board carries 6,773 components and 3,946 named nets across 23,610 pads, with 1,457 test and probe points marked in amber for when you want to measure rather than desolder. About 100% of the components are surface-mount, so the top and bottom side filter is usually the difference between finding a part in one pass and searching both faces.
The schematic is 131 pages and covers the usual blocks you would expect on a board this size — input power, PPBUS/G3 hot, rails, clock, storage, display and audio output. The page index under the viewer gives you the heading on each sheet, so you can jump straight to the block you are chasing instead of scrolling.
This is the logic board fitted to the A2338. Check the board number before you order parts: several of these machines shipped with more than one board revision, and a component taken off the wrong revision frequently has the same designator and a different footprint.
Frequently asked about the MacBook A2338 (820-01814)
What board number is the MacBook A2338 (820-01814)?
The MacBook A2338 (820-01814) uses logic board 820-01814, the board fitted to the A2338. There is more than one revision of some of these boards, so check the number on the board itself against the one on this page before you order a part — a component from a different revision will often not fit or will not reference the same nets.
How many components and nets are on the MacBook A2338 (820-01814)?
The board file records 6,773 components (6,749 surface-mount, 24 through-hole), 3,946 named nets and 23,610 pads, plus 1,457 test and probe points. The board measures 334.54 × 121.26 mm. Roughly 100% of the parts are surface-mount, which is why the top and bottom side filter matters — a lot of this board is only reachable from one face.
How do I use this MacBook A2338 (820-01814) boardview?
Type a designator such as a component reference, or a net name, into the search box above. A net name takes priority and highlights every pad on that net across the whole board. Clicking a component outlines it in white and lists every pad it has with the net each one belongs to; clicking one of those nets jumps the highlight to the whole rail. Use the side filter to isolate the top or bottom face, and the designator toggle to hide the reference text when you are zoomed out.
Does the MacBook A2338 (820-01814) come with a schematic?
Yes — the full 131-page schematic is embedded above and downloadable as a 24.6 MB PDF. The page index under the viewer lists the page headings so you can jump to a circuit rather than scrolling through every page. The schematic's text layer is also published as text on this page, which means you can search it with Ctrl+F on any browser, including the ones where a PDF in a frame refuses to be searched.
Can I download the MacBook A2338 (820-01814) boardview file?
Yes. The original 1.1 MB BoardView file is linked below under downloads, named macbook-a2338-820-01814.brd. Open it in BoardViewer or any other tool that reads the .brd format. The interactive viewer on this page is for looking things up quickly; the .brd is what you want when you are at the bench with the board on the mat.
Schematic text — searchable without opening the PDF
A PDF inside a frame is invisible to a crawler and often unsearchable in the browser. Here is the schematic’s text layer as plain text, so you can use Ctrl+F on this page to find a rail name, a component reference or a page heading.
8 7 6 5 4 3 2 1 From Intel EDS PEG RCOMP Range = 24.76,25.25 Voltage = VCCIO (Page 121, Note 3) PPVCCIO_S0_CPU 5 8 10 115 U0500 1 R0510 U0500 24.9 1% CFL-H-BDGADR4-IL 1/16W CFL-H-BDGADR4-IL MF-LF 118 13 IN DMI_S2N_N<0> E8 DMI_RXN0 45W PEG_RCOMP G2 CPU_PEG_RCOMP 402 117 NC_DDI1_ML_C_N<0> K37 DDI1_TXN0 45W EDP_AUXN B26 DP_INT_IG_AUX_N 93 118 118 13 IN DMI_S2N_N<1> F6 DMI_RXN1 SYM 1 OF 13 PEG_GPU_D2R_N<0> 117 NC_DDI1_ML_C_P<0> K36 DDI1_TXP0 EDP_AUXP C26 DP_INT_IG_AUX_P 93 118 118 13 IN DMI_S2N_N<2> 2 117 NC_DDI1_ML_C_N<1> J34 DDI1_TXN1 SYM 11 OF 13 E5 DMI_RXN2 CRITICAL PEG_RXN0 D25 PLACE_NEAR=U0500.G2:5mm CRITICAL IN 117 118 13 IN DMI_S2N_N<3> J9 DMI_RXN3 OMIT_TABLE PEG_RXN1 F24 PEG_GPU_D2R_N<1> IN 117 117 NC_DDI1_ML_C_P<1> J35 DDI1_TXP1 OMIT_TABLE PEG_RXN2 D23 PEG_GPU_D2R_N<2> IN 117 117 NC_DDI1_ML_C_N<2> H36 DDI1_TXN2 EDP EDP_TXN0 E29 DP_INT_IG_ML_N<0> 93 118 D 117 NC_DDI1_ML_C_P<2> H37 DDI1_TXP2 EDP_TXN1 E28 D 118 13 IN DMI_S2N_P<0> D8 DMI_RXP0 PEG_RXN3 F22 PEG_GPU_D2R_N<3> IN 117 DP_INT_IG_ML_N<1> 93 118 118 13 IN DMI_S2N_P<1> E6 DMI_RXP1 PEG_RXN4 D21 PEG_GPU_D2R_N<4> IN 117 117 NC_DDI1_ML_C_N<3> J38 DDI1_TXN3 EDP_TXN2 B29 DP_INT_IG_ML_N<2> 93 118 118 13 IN DMI_S2N_P<2> D5 DMI_RXP2 PEG_RXN5 F20 PEG_GPU_D2R_N<5> IN 117 117 NC_DDI1_ML_C_P<3> J37 DDI1_TXP3 EDP_TXN3 B28 DP_INT_IG_ML_N<3> 93 118 118 13 IN DMI_S2N_P<3> J8 DMI_RXP3 PEG_RXN6 D19 PEG_GPU_D2R_N<6> IN 117 EDP_TXP0 D29 DP_INT_IG_ML_P<0> 93 118 PEG_RXN7 F18 PEG_GPU_D2R_N<7> IN 117 EDP_TXP1 F28 DP_INT_IG_ML_P<1> 93 118 DMI_N2S_N<0> A8 DMI_TXN0 DMI PEG_RXN8 E17 PCIE_TBT_X_D2R_N<0> IN 117 117 NC_DDI2_ML_C_N<0> H33 DDI2_TXN0 DIGITAL DISPLAY INTERFACES EDP_TXP2 A29 DP_INT_IG_ML_P<2> 93 118 PPVCCIO_S0_CPU 5 8 10 DMI_N2S_N<1> B6 DMI_TXN1 PEG_RXN9 E16 PCIE_TBT_X_D2R_N<1> IN 117 117 NC_DDI2_ML_C_P<0> H34 DDI2_TXP0 EDP_TXP3 C28 DP_INT_IG_ML_P<3> 93 118 115 DMI_N2S_N<2> A5 DMI_TXN2 PEG_RXN10 E15 PCIE_TBT_X_D2R_N<2> IN 117 117 NC_DDI2_ML_C_N<1> G38 DDI2_TXN1 1 R0530 118 13 OUT DMI_N2S_N<3> B4 DMI_TXN3 PEG_RXN11 E14 PCIE_TBT_X_D2R_N<3> IN 117 117 NC_DDI2_ML_C_P<1> F37 DDI2_TXP1 118 13 OUT PEG_RXN12 E13 PCIE_TBT_T_D2R_N<0> IN 117 117 NC_DDI2_ML_C_N<2> F35 DDI2_TXN2 24.9 118 13 OUT B8 DMI_TXP0 PEG_RXN13 E12 PCIE_TBT_T_D2R_N<1> IN 117 117 NC_DDI2_ML_C_P<2> F34 DDI2_TXP2 118 13 OUT C6 DMI_TXP1 PEG_RXN14 E11 PCIE_TBT_T_D2R_N<2> IN 117 117 NC_DDI2_ML_C_N<3> E36 DDI2_TXN3 1% B5 DMI_TXP2 PEG_RXN15 E10 PCIE_TBT_T_D2R_N<3> IN 117 117 NC_DDI2_ML_C_P<3> E37 DDI2_TXP3 1/16W 118 13 OUT DMI_N2S_P<0> DISP_RCOMP D37 CPU_EDP_RCOMP MF-LF 118 13 OUT DMI_N2S_P<1> EDP_DISP_UTIL A33 NC 402 118 13 OUT DMI_N2S_P<2> 2 PLACE_NEAR=U0500.D37:5mm 118 13 OUT DMI_N2S_P<3> D4 DMI_TXP3 117 NC_DDI3_ML_N<2> E33 DDI3_TXN2 PEG_RXP0 E25 PEG_GPU_D2R_P<0> IN 117 117 NC_DDI3_ML_P<2> F33 DDI3_TXP2 DDI1_AUXN E27 NC_DDI1_AUXCH_C_N 117 PEG_RXP1 E24 PEG_GPU_D2R_P<1> IN 117 117 NC_DDI3_ML_N<3> B33 DDI3_TXN3 DDI1_AUXP D27 PEG_RXP2 E23 PEG_GPU_D2R_P<2> IN 117 117 NC_DDI3_ML_P<3> C33 DDI3_TXP3 NC_DDI1_AUXCH_C_P 117 PEG_RXP3 E22 PEG_GPU_D2R_P<3> IN 117 117 NC_DDI3_ML_N<0> D34 DDI3_TXN0 DDI2_AUXN E26 NC_DDI2_AUXCH_C_N 117 PEG_RXP4 E21 PEG_GPU_D2R_P<4> IN 117 117 NC_DDI3_ML_P<0> C34 DDI3_TXP0 DDI2_AUXP F26 PEG_RXP5 E20 PEG_GPU_D2R_P<5> IN 117 117 NC_DDI3_ML_N<1> B34 DDI3_TXN1 NC_DDI2_AUXCH_C_P 117 PEG_RXP6 E19 PEG_GPU_D2R_P<6> IN 117 117 NC_DDI3_ML_P<1> B36 DDI3_TXP1 DDI3_AUXN B27 PEG_RXP7 E18 PEG_GPU_D2R_P<7> IN 117 DDI3_AUXP A27 NC_DDI3_AUXCH_N 117 PEG_RXP8 D17 PCIE_TBT_X_D2R_P<0> IN 117 Port D pins out of order PEG_RXP9 F16 PCIE_TBT_X_D2R_P<1> IN 117 to match Intel symbol. NC_DDI3_AUXCH_P 117 PEG_RXP10 D15 PCIE_TBT_X_D2R_P<2> IN 117 PCI EXPRESS BASED INTERFACE SIGNALS PEG_RXP11 F14 PCIE_TBT_X_D2R_P<3> IN 117 C PEG_RXP12 D13 PCIE_TBT_T_D2R_P<0> IN 117 C PEG_RXP13 F12 PCIE_TBT_T_D2R_P<1> IN 117 PEG_RXP14 D11 PCIE_TBT_T_D2R_P<2> IN 117 PEG_RXP15 F10 PCIE_TBT_T_D2R_P<3> IN 117 PEG_TXN0 A25 PEG_GPU_R2D_C_N<0> OUT 117 PEG_TXN1 C24 PEG_GPU_R2D_C_N<1> OUT 117 PEG_TXN2 A23 PEG_GPU_R2D_C_N<2> OUT 117 U0500 Impedance Spectrum Tool PEG_TXN3 C22 PEG_GPU_R2D_C_N<3> OUT 117 PEG_TXN4 A21 PEG_GPU_R2D_C_N<4> OUT 117 TP-P5 TP0501 TP 1 CPU_DC_B2_C1 B2 RSVD CFL-H-DDR4-IL IST_TRIG E3 CPU_IST_TRIG 1 ATP0506 PEG_TXN5 C20 PEG_GPU_R2D_C_N<5> OUT 117 TP-P5 TP0502 TP 1 CPU_DC_B38_C38 1TP-P6 ATP0507 PEG_TXN6 A19 PEG_GPU_R2D_C_N<6> OUT 117 TP-P5 TP0503 TP 1 B38 RSVD BGA PEG_TXN7 C18 PEG_GPU_R2D_C_N<7> OUT 117 TP-P5 TP0504 TP 1 CPU_DC_BR2_BR1 45W TP-P6 PEG_TXN8 B17 PCIE_TBT_X_R2D_C_N<0> OUT 117 TP-P5 TP0505 TP 1 CPU_DC_C1_B2 PEG_TXN9 B16 PCIE_TBT_X_R2D_C_N<1> OUT 117 CPU_DC_C38_B38 SYM 13 OF 13 PEG_TXN10 B15 PCIE_TBT_X_R2D_C_N<2> OUT 117 PEG_TXN11 B14 PCIE_TBT_X_R2D_C_N<3> OUT 117 NC BP1 RSVD PEG_TXN12 B13 PCIE_TBT_T_R2D_C_N<0> OUT 117 BR2 RSVD PROC_TRIGIN H23 PCH_CPU_TRIGGER PLACE_NEAR=TP0506.1:5mm PROC_TRIGOUT J23 CPU_PCH_TRIGGER_R C1 RSVD IN 13 PROC_AUDIO_CLK G27 PCH_DISPA_BCLK 5 C38 RSVD PROC_AUDIO_SDI G25 PCH_DISPA_SDO IN 20 NC BR33 SKTOCC* IN 20 PEG_TXN13 B12 PCIE_TBT_T_R2D_C_N<1> OUT 117 NC AT13 ZVM* PROC_AUDIO_SDO G29 CPU_PROC_AUD_SDO_R 5 PEG_TXN14 B11 PCIE_TBT_T_R2D_C_N<2> OUT 117 NC AW13 MSM* DDR_VTT_CNTL BT13 PM_MEMVTT_EN OUT 74 119 PEG_TXN15 B10 PCIE_TBT_T_R2D_C_N<3> OUT 117 PM_DOWN BP31 CPU_PCH_PM_DOWN_R 5 PEG_TXP0 B25 PEG_GPU_R2D_C_P<0> OUT 117 PEG_TXP1 B24 PEG_GPU_R2D_C_P<1> OUT 117 PEG_TXP2 B23 PEG_GPU_R2D_C_P<2> OUT 117 PEG_TXP3 B22 PEG_GPU_R2D_C_P<3> OUT 117 B PEG_TXP4 B21 PEG_GPU_R2D_C_P<4> OUT 117 Each corner of CPU has two testpoints. B PEG_TXP5 B20 PEG_GPU_R2D_C_P<5> OUT 117 Other corner test signals connected in PEG_TXP6 B19 PEG_GPU_R2D_C_P<6> OUT 117 daisy-chain fashion. Continuity should PEG_TXP7 B18 PEG_GPU_R2D_C_P<7> OUT 117 exist between both TP's on each corner. PEG_TXP8 A17 PCIE_TBT_X_R2D_C_P<0> OUT 117 PEG_TXP9 C16 PCIE_TBT_X_R2D_C_P<1> OUT 117 PEG_TXP10 A15 PCIE_TBT_X_R2D_C_P<2> OUT 117 PEG_TXP11 C14 PCIE_TBT_X_R2D_C_P<3> OUT 117 5 CPU_PCH_TRIGGER_R R0524 OUT 13 PEG_TXP12 A13 PCIE_TBT_T_R2D_C_P<0> OUT 117 PEG_TXP13 C12 PCIE_TBT_T_R2D_C_P<1> OUT 117 1 30 2 CPU_PCH_TRIGGER PEG_TXP14 A11 PCIE_TBT_T_R2D_C_P<2> OUT 117 PEG_TXP15 C10 PCIE_TBT_T_R2D_C_P<3> OUT 117 5% 1/20W MF 201 5 CPU_PCH_PM_DOWN_R R0525 OUT 13 1 20 2 CPU_PCH_PM_DOWN 5% 1/20W MF 201 5 CPU_PROC_AUD_SDO_R 1R025026 2 PCH_DISPA_SDI OUT 20 5% 1/20W MF 201 A SYNC_MASTER=ZIFENG SYNC_DATE=09/07/2017 A PAGE TITLE CPU DMI/PEG/FDI/RSVD DRAWING NUMBER SIZE Apple Inc. 051-02888 D NOTICE OF PROPRIETARY PROPERTY: REVISION THE INFORMATION CONTAINED HEREIN IS THE 1.0.0 PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: BRANCH I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT EVT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED PAGE 5 OF 200 BOM_COST_GROUP=CPU & CHIPSET SHEET 5 OF 131 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 115 11 8 PP1V05_S0SW U0500 115 46 11 8 PP1V05_S3 CFL-H-BDGADR4-IL NC BN1 PROC_SELECT* 45W DDR_RCOMP0 G1 CPU_SM_RCOMP<0> DDR_RCOMP1 H1 CPU_SM_RCOMP<1> NOSTUFF SYM 2 OF 13 DDR_RCOMP2 J2 CPU_SM_RCOMP<2> 1 R0605 1 R0604 1K 1K 1 R0601 77 OUT CPU_CATERR_L BM30 CATERR* THERMAL CRITICAL DDR3 1% 1K 1% PLACE_NEAR=46U013500B.BI R30:5CmPmU_PECI OMIT_TABLE 1/16W 1/16W 1% R0603 BT34 PECI 1 R0614 1 R0613 1 R0612 MF-LF MF-LF 1/16W 402 2 402 MF-LF 100 121 121 402 2 499 (IPU) PROC_PRDY* BP27 XDP_CPU_PRDY_L 1% 1% 1% 2 (IPU) PROC_PREQ* BL30 XDP_CPU_PREQ_L 46 IN CPU_PROCHOT_L 1 2 CPU_PROCHOT_R_L BR30 PROCHOT* OUT 13 18 121 1/16W 1/16W 1/16W IN 13 18 121 MF-LF MF-LF MF-LF 1% 201 2 402 402 2 402 D D 1/20W PM_THRMTRIP_L J31 THERMTRIP* 2 MF 119 46 OUT (IPD) PROC_TCK BR28 XDP_CPU_TCK IN 18 121 13 IN PM_SYNC BM34 PM_SYNC (IPU) PROC_TMS BP28 XDP_CPU_TMS IN 18 121 13 IN CPU_RESET_L BP35 RESET* (IPU) PROC_TRST* BP30 XDP_CPU_TRST_L IN 13 18 121 121 119 13 IN CPU_PWRGD BT31 PROCPWRGD PWR (IPU) PROC_TDI BL32 XDP_CPU_TDI IN 18 121 PROC_TDO BT28 XDP_CPU_TDO OUT 18 121 JTAG CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4 CPU_CLK24M_NSSC_CLK_N D31 CLK24N (IPU) BPM0* BR27 XDP_BPM_L<0> BI 18 CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED CPU_CLK24M_NSSC_CLK_P E31 CLK24P (IPU) BPM1* BT27 XDP_BPM_L<1> BI 18 CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED 118 12 IN (IPU) BPM2* BM31 XDP_BPM_L<2> BI 18 118 12 IN BI 18 CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED CPU_CLK100M_PCIBCLK_N C36 PCI_BCLKN CLOCK (IPU) BPM3* BT30 XDP_BPM_L<3> CPU_CLK100M_PCIBCLK_P D35 PCI_BCLKP 118 12 IN 118 12 IN These can be placed close to J1800 and only for debug access 118 12 IN CPU_CLK100M_BCLK_N A32 BCLKN 118 12 IN CPU_CLK100M_BCLK_P B31 BCLKP CPU_CFG<16> 6 18 PLACE_NEAR=U0500.BT31:157mm CPU_CFG<9> 6 18 R0611 1 CPU_CFG<3> 6 18 10K 5% CPU_CFG<1> 6 18 1/16W MF-LF CPU_CFG<0> 6 18 P2MM 402 NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF SM CPU_RSVD_R14 2 R0649 1 R0648 1 1 R0643 R0641 1 1 R0640 PP0600 PP 1 6 1K 1K 1K 1K 1K 5% 5% 5% P2MM 1/20W 1/20W 5% 1/20W 5% SM 1/20W 1/20W CPU_RSVD_N29 6 PP0601 PP 1 C MF MF MF MF MF C 201 201 201 201 201 P2MM B SM 2 2 2 2 2 CPU_RSVD_AE29 PP0602 PP 1 6 P2MM SM CPU_RSVD_AA14 6 PP0603 PP 1 U0500 CFL-H-DDR4-IL CRITICAL CPU_CFG<7> 6 18 OMIT_TABLE 4B5GAW CPU_CFG<6> 6 18 CPU_CFG<5> 6 18 SYM 12 OF 13 RESERVED CPU_CFG<4> 6 18 CPUCFG6_PD CPUCFG5_PD CPU_CFG<2> 6 18 NOSTUFF R0646 1 1 R0645 EDP:YES NOSTUFF TP0619 TP-P6 1 TP_CPU_RSVD_TP_D1 D1 RSVD_TP CFG_RCOMP BT25 CPU_CFG_RCOMP R0647 1 1K 1K R0644 1 1 R0642 A V30 VSS CFG16 BP23 5% V12 VSS CFG18 BN22 1K 1/20W 5% 1K 1K V29 VSS CFG17 BN23 CPU_CFG<16> 6 18 5% 1/20W 5% CFG19 BP22 CPU_CFG<18> 1/20W MF MF 1/20W 5% CPU_CFG<17> 18 201 201 1/20W CPU_CFG<19> MF MF MF 201 2 2 201 201 2 2 2 1 TP TP0617 TP-P5 TP0618 TP-P5 1 TP 115 58 8 PPVCC_S0_CPU Y35 VCC (IPU) RSVD AU13 NC 1 R0690 6 CPU_RSVD_R14 R14 RSVD RSVD AY13 NC 49.9 6 CPU_RSVD_N29 N29 RSVD 6 CPU_RSVD_AE29 AE29 RSVD (IPU) RSVD J24 NC 1% 1/16W RSVD J3 NC MF-LF 402 2 6 CPU_RSVD_AA14 AA14 RSVD RSVD BN33 NC B TP0601 TP-P6 TP0602 TP0603 ATP-P6 1 CPU_CFG<0> BN25 CFG0 (IPU) RSVD BR35 NC TP0604 ATP-P6 1 CPU_CFG<1> BN27 CFG1 (IPU) TP0605 ATP-P6 1 CPU_CFG<2> BN26 CFG2 (IPU) RSVD BR31 NC TP0606 ATP-P6 1 CPU_CFG<3> BN28 CFG3 (IPU) TP0607 ATP-P6 1 CPU_CFG<4> BR20 CFG4 (IPU) RSVD BN35 NC TP0608 ATP-P6 1 CPU_CFG<5> BM20 CFG5 (IPU) TP0609 ATP-P6 1 CPU_CFG<6> BT20 CFG6 (IPU) RSVD C30 NC TP-P5 1 TP TP0620 TP0610 ATP-P6 1 CPU_CFG<7> BP20 CFG7 (IPU) 1 TP0600 TP0611 ATP-P6 1 CPU_CFG<8> BR23 CFG8 (IPU) RSVD_TP BT2 TP_CPU_RSVD_TP_BT2 TP TP0612 ATP-P6 1 CPU_CFG<9> BR22 CFG9 (IPU) RSVD_TP BR1 CPU_DC_BR1_BR2 TP-P5 TP0613 ATP-P6 1 CPU_CFG<10> BT23 CFG10(IPU) TP0614 ATP-P6 1 CPU_CFG<11> BT22 CFG11(IPU) VSS W3 TP0615 ATP-P6 1 CPU_CFG<12> BM19 CFG12(IPU) VSS W2 TP0616 ATP-P6 1 CPU_CFG<13> BR19 CFG13(IPU) VSS V6 ATP-P6 1 CPU_CFG<14> BP19 CFG14(IPU) VSS W1 A 1 CPU_CFG<15> BT19 CFG15(IPU) NC G3 RSVD RSVD H24 NC NC G13 RSVD RSVD E30 NC RSVD F30 NC A BOM GROUP BOM OPTIONS TABLE_BOMGROUP_HEAD SYNC_MASTER=j380_mlb SYNC_DATE=02/09/2017 A TABLE_BOMGROUP_ITEM CPUPEG:X8X8 CPUCFG5_PD TABLE_BOMGROUP_ITEM PAGE TITLE CPUPEG:X8X4X4 CPUCFG6_PD,CPUCFG5_PD BOM_COST_GROUP=CPU & CHIPSET CPU Clock/Misc/JTAG/CFG To use PEG X16 configuration, simply remove CPUPEG:X8X8 and CPUPEG:X8X4X4 from BOMs. 3 DRAWING NUMBER SIZE Apple Inc. 051-02888 D NOTICE OF PROPRIETARY PROPERTY: REVISION THE INFORMATION CONTAINED HEREIN IS THE 1.0.0 PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: BRANCH I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT EVT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED PAGE 6 OF 200 SHEET 6 OF 131 8 7 6 5 4 2 1 8 7 6 5 4 3 2 1 125 BI MEM_A_DQ<45> BR6 DDR0_DQ0 U0B5GA00 DDR0_CKN0 AG2 MEM_A_CLK_N<0> OUT 22 23 26 118 125 BI MEM_B_DQ<22> BT11 DDR1_DQ0 U0500 BGA DDR1_CKN0 AN9 MEM_B_CLK_N<0> OUT 24 25 26 118 125 BI MEM_A_DQ<41> BT6 DDR0_DQ1 DDR0_CKP0 AG1 MEM_A_CLK_P<0> OUT 22 23 26 118 125 BI MEM_B_DQ<16> BR11 DDR1_DQ1 SYM 4 OF 13 AM9 MEM_B_CLK_P<0> OUT 24 25 26 118 125 BI MEM_A_DQ<44> BP3 DDR0_DQ2 SYM 3 OF 13 DDR0_CKE0 AT1 MEM_A_CKE<0> OUT 22 23 26 125 BI MEM_B_DQ<18> DDR1_CKP0 AT8 MEM_B_CKE<0> OUT 24 25 26 125 BI MEM_A_DQ<40> BR3 DDR0_DQ3 125 BI MEM_B_DQ<17> BT9 DDR1_DQ2 125 BI MEM_A_DQ<47> BN5 DDR0_DQ4 45W NC_MEM_A_CLK_N<1> 125 BI MEM_B_DQ<20> BR8 DDR1_DQ3 AM8 NC_MEM_B_CLK_N<1> 125 BI MEM_A_DQ<43> BP6 DDR0_DQ5 NC_MEM_A_CLK_P<1> 125 BI MEM_B_DQ<23> BP11 DDR1_DQ4 AM7 NC_MEM_B_CLK_P<1> 125 BI MEM_A_DQ<46> BP2 DDR0_DQ6 CFL-H-DDR4-IL 125 BI MEM_B_DQ<19> BN11 DDR1_DQ5 45W DDR1_CKE0 AT10 MEM_B_CKE<1> 125 BI MEM_B_DQ<21> BP8 DDR1_DQ6 CRITICAL DDR0_CKN1 AK1 OUT 26 118 125 BI MEM_B_DQ<11> BN8 DDR1_DQ7 CFL-H-DDR4-IL AM10 NC OUT 26 118 125 BI MEM_B_DQ<14> AM11 NC OMIT_TABLE DDR0_CKP1 AK2 125 BI MEM_B_DQ<9> DDR1_CKN1 AT7 OUT 26 118 125 BI MEM_B_DQ<12> CRITICAL OUT 26 118 125 BI MEM_A_DQ<42> BN3 DDR0_DQ7 DDR0_CKE1 AT2 MEM_A_CKE<1> OUT 22 23 26 OUT 24 25 26 DDR1_CKP1 125 BI MEM_A_DQ<49> BL4 DDR0_DQ8 DDR0_CKN2 AK3 NC OMIT_TABLE D BL5 DDR0_DQ9 BL2 DDR0_DQ10 DDR1_CKE1 BM1 DDR0_DQ11 D 125 BI MEM_A_DQ<50> DDR0_CKP2 AL3 NC BL12 DDR1_DQ8 DDR1_CKN2 BL11 DDR1_DQ9 DDR1_CKP2 125 BI MEM_A_DQ<53> DDR0_CKE2 AT3 NC_MEM_A_CKE<2> OUT 26 BL8 DDR1_DQ10 DDR1_CKE2 125 BI MEM_A_DQ<51> BJ8 DDR1_DQ11 NC_MEM_B_CKE<2> OUT 26 125 BI MEM_A_DQ<52> BK4 DDR0_DQ12 DDR0_CKN3 AL1 NC 125 BI MEM_A_DQ<54> BK5 DDR0_DQ13 DDR0_CKP3 AL2 NC 125 BI MEM_B_DQ<15> BJ11 DDR1_DQ12 DDR1_CKN3 AJ11 NC 125 BI MEM_A_DQ<55> BK1 DDR0_DQ14 DDR0_CKE3 AT5 NC_MEM_A_CKE<3> OUT 26 125 BI MEM_B_DQ<13> BJ10 DDR1_DQ13 DDR1_CKP3 AJ10 NC 125 BI MEM_A_DQ<48> BK2 DDR0_DQ15 125 BI MEM_B_DQ<8> BL7 DDR1_DQ14 DDR1_CKE3 AT11 NC_MEM_B_CKE<3> OUT 26 125 BI MEM_A_DQ<62> BG4 DDR0_DQ16 DDR0_CS0* AD5 MEM_A_CS_L<0> OUT 22 23 26 125 BI MEM_B_DQ<10> BJ7 DDR1_DQ15 125 BI MEM_A_DQ<63> BG5 DDR0_DQ17 DDR0_CS1* AE2 MEM_A_CS_L<1> OUT 22 23 26 125 BI MEM_B_DQ<6> BG11 DDR1_DQ16 DDR1_CS0* AF11 MEM_B_CS_L<0> OUT 24 25 26 125 BI MEM_A_DQ<57> BF4 DDR0_DQ18 DDR0_CS2* AD2 NC 125 BI MEM_B_DQ<5> BG10 DDR1_DQ17 DDR1_CS1* AE7 MEM_B_CS_L<1> OUT 24 25 26 125 BI MEM_A_DQ<56> BF5 DDR0_DQ19 DDR0_CS3* AE5 NC 125 BI MEM_B_DQ<2> BG8 DDR1_DQ18 DDR1_CS2* AF10 NC 125 BI MEM_A_DQ<60> BG2 DDR0_DQ20 DDR0_ODT0 AD3 MEM_A_ODT<0> 125 BI MEM_B_DQ<3> BF8 DDR1_DQ19 DDR1_CS3* AE10 NC 125 BI MEM_A_DQ<61> BG1 DDR0_DQ21 MEMORY CHANNEL DDR0 125 BI MEM_A_DQ<58> BF1 DDR0_DQ22 MEMORY CHANNEL DDR1DDR0_ODT1 AE4MEM_A_ODT<1>OUT22 23 26125 BIMEM_B_DQ<7>BF11 DDR1_DQ20DDR1_ODT0 AF7MEM_B_ODT<0>OUT24 25 26 125 BI MEM_A_DQ<59> BF2 DDR0_DQ23 OUT 22 23 26 125 BI MEM_B_DQ<1> BF10 DDR1_DQ21 MEM_B_ODT<1> OUT 24 25 26 125 BI MEM_A_DQ<35> BD2 DDR0_DQ24 125 BI MEM_B_DQ<4> BG7 DDR1_DQ22 DDR1_ODT1 AE8 DDR0_ODT2 AE1 NC 125 BI MEM_B_DQ<0> BF7 DDR1_DQ23 DDR0_ODT3 AD4 NC 125 BI MEM_B_DQ<25> BB11 DDR1_DQ24 DDR1_ODT2 AE9 NC DDR1_ODT3 AE11 NC 125 BI MEM_A_DQ<37> BD1 DDR0_DQ25 125 BI MEM_A_DQ<33> BC4 DDR0_DQ26 125 BI MEM_B_DQ<30> BC11 DDR1_DQ25 125 BI MEM_A_DQ<32> BC5 DDR0_DQ27 125 BI MEM_B_DQ<29> BB8 DDR1_DQ26 125 BI MEM_A_DQ<39> BD5 DDR0_DQ28 125 BI MEM_B_DQ<26> BC8 DDR1_DQ27 125 BI MEM_A_DQ<38> BD4 DDR0_DQ29 VSS U38 125 BI MEM_B_DQ<31> BC10 DDR1_DQ28 125 BI MEM_A_DQ<34> BC1 DDR0_DQ30 125 BI MEM_B_DQ<24> BB10 DDR1_DQ29 VSS Y38 125 BI MEM_A_DQ<36> BC2 DDR0_DQ31 125 BI MEM_B_DQ<28> BC7 DDR1_DQ30 125 BI MEM_A_DQ<26> AB1 DDR0_DQ32 125 BI MEM_B_DQ<27> BB7 DDR1_DQ31 125 BI MEM_A_DQ<24> AB2 DDR0_DQ33 125 BI MEM_B_DQ<38> AA11 DDR1_DQ32 125 BI MEM_A_DQ<30> AA4 DDR0_DQ34 125 BI MEM_B_DQ<39> AA10 DDR1_DQ33 C 125 BI MEM_A_DQ<31> AA5 DDR0_DQ35 125 BI MEM_B_DQ<33> AC11 DDR1_DQ34 C 125 BI MEM_A_DQ<25> AB5 DDR0_DQ36 125 BI MEM_B_DQ<34> AC10 DDR1_DQ35 125 BI MEM_A_DQ<29> AB4 DDR0_DQ37 125 BI MEM_B_DQ<36> AA7 DDR1_DQ36 125 BI MEM_A_DQ<28> AA2 DDR0_DQ38 125 BI MEM_B_DQ<37> AA8 DDR1_DQ37 125 BI MEM_A_DQ<27> AA1 DDR0_DQ39 125 BI MEM_B_DQ<35> AC8 DDR1_DQ38 125 BI MEM_A_DQ<1> V5 DDR0_DQ40 125 BI MEM_B_DQ<32> AC7 DDR1_DQ39 125 BI MEM_A_DQ<4> V2 DDR0_DQ41 125 BI MEM_B_DQ<56> W8 DDR1_DQ40 125 BI MEM_A_DQ<2> U1 DDR0_DQ42 DDR0_ECC0 BA2 NC 125 BI MEM_B_DQ<57> W7 DDR1_DQ41 125 BI MEM_A_DQ<3> U2 DDR0_DQ43 DDR0_ECC1 BA1 NC 125 BI MEM_A_DQ<0> V1 DDR0_DQ44 DDR0_ECC2 AY4 NC 125 BI MEM_B_DQ<60> V10 DDR1_DQ42 DDR1_ECC0 AW11 NC 125 BI MEM_A_DQ<5> V4 DDR0_DQ45 DDR0_ECC3 AY5 NC 125 BI MEM_B_DQ<58> V11 DDR1_DQ43 DDR1_ECC1 AY11 NC 125 BI MEM_A_DQ<7> U5 DDR0_DQ46 DDR0_ECC4 BA5 NC 125 BI MEM_B_DQ<59> W11 DDR1_DQ44 DDR1_ECC2 AY8 NC 125 BI MEM_A_DQ<6> U4 DDR0_DQ47 DDR0_ECC5 BA4 NC 125 BI MEM_B_DQ<61> W10 DDR1_DQ45 DDR1_ECC3 AW8 NC 125 BI MEM_A_DQ<13> R2 DDR0_DQ48 DDR0_ECC6 AY1 NC 125 BI MEM_B_DQ<62> V7 DDR1_DQ46 DDR1_ECC4 AY10 NC 125 BI MEM_A_DQ<8> P5 DDR0_DQ49 DDR0_ECC7 AY2 NC 125 BI MEM_B_DQ<63> V8 DDR1_DQ47 DDR1_ECC5 AW10 NC 125 BI MEM_A_DQ<14> R4 DDR0_DQ50 125 BI MEM_B_DQ<54> R11 DDR1_DQ48 DDR1_ECC6 AY7 NC 125 BI MEM_B_DQ<49> P11 DDR1_DQ49 DDR1_ECC7 AW7 NC MEM_A_DQ<9> P4 DDR0_DQ51 125 BI MEM_B_DQ<48> P7 DDR1_DQ50 125 BI MEM_A_DQ<15> R5 DDR0_DQ52 DDR0_DQSN0 BR5 MEM_A_DQS_N<5> 125 BI MEM_A_DQ<10> P2 DDR0_DQ53 BI 125 MEM_B_DQ<51> R8 DDR1_DQ51 125 BI MEM_A_DQ<11> R1 DDR0_DQ54 DDR0_DQSN1 BL3 MEM_A_DQS_N<6> BI 125 125 BI MEM_B_DQ<52> R10 DDR1_DQ52 DDR1_DQSN0 BN9 MEM_B_DQS_N<2> BI 125 125 BI MEM_A_DQ<12> P1 DDR0_DQ55 BI 125 125 BI MEM_B_DQ<55> P10 DDR1_DQ53 DDR1_DQSN1 BL9 MEM_B_DQS_N<1> BI 125 125 BI MEM_A_DQ<23> M4 DDR0_DQ56 DDR0_DQSN2 BG3 MEM_A_DQS_N<7> BI 125 125 BI MEM_B_DQ<50> R7 DDR1_DQ54 DDR1_DQSN2 BG9 MEM_B_DQS_N<0> BI 125 125 BI MEM_A_DQ<22> M1 DDR0_DQ57 BI 125 125 BI MEM_B_DQ<53> DDR1_DQSN3 BC9 MEM_B_DQS_N<3> BI 125 125 BI MEM_A_DQ<17> L4 DDR0_DQ58 DDR0_DQSN3 BD3 MEM_A_DQS_N<4> BI 125 125 BI MEM_B_DQ<41> P8 DDR1_DQ55 DDR1_DQSN4 AC9 MEM_B_DQS_N<4> BI 125 125 BI MEM_A_DQ<18> L2 DDR0_DQ59 BI 125 125 BI MEM_B_DQ<46> L11 DDR1_DQ56 DDR1_DQSN5 MEM_B_DQS_N<7> BI 125 125 BI MEM_A_DQ<20> M5 DDR0_DQ60 DDR0_DQSN4 AA3 MEM_A_DQS_N<3> BI 125 125 BI MEM_B_DQ<43> M11 DDR1_DQ57 DDR1_DQSN6 W9 MEM_B_DQS_N<6> BI 125 125 BI 125 BI MEM_B_DQ<44> L7 DDR1_DQ58 DDR1_DQSN7 R9 MEM_B_DQS_N<5> BI 125 DDR0_DQSN5 U3 MEM_A_DQS_N<0> 125 BI MEM_B_DQ<42> M8 DDR1_DQ59 DDR1_DQSN8 M9 125 BI MEM_B_DQ<47> L10 DDR1_DQ60 AY9 NC BI 125 DDR0_DQSN6 P3 MEM_A_DQS_N<1> 125 BI MEM_B_DQ<40> M10 DDR1_DQ61 BI 125 125 BI MEM_B_DQ<45> M7 DDR1_DQ62 BI 125 DDR0_DQSN7 L3 MEM_A_DQS_N<2> 125 BI L8 DDR1_DQ63 DDR0_DQSN8 BA3 NC B 125 BI MEM_A_DQ<21> M2 DDR0_DQ61 DDR0_DQSP0 BP5 MEM_A_DQS_P<5> BI 125 DDR1_DQSP0 BP9 MEM_B_DQS_P<2> B 125 BI MEM_A_DQ<16> L5 DDR0_DQ62 DDR0_DQSP1 BK3 MEM_A_DQS_P<6> BI 125 DDR1_DQSP1 BJ9 MEM_B_DQS_P<1> L1 DDR0_DQ63 DDR0_DQSP2 BF3 MEM_A_DQS_P<7> BI 125 DDR1_DQSP2 BF9 MEM_B_DQS_P<0> 125 BI MEM_A_DQ<19> DDR0_DQSP3 BC3 MEM_A_DQS_P<4> BI 125 26 23 22 OUT MEM_A_PAR AG3 DDR0_PAR DDR0_DQSP4 AB3 MEM_A_DQS_P<3> BI 125 DDR1_DQSP3 BB9 MEM_B_DQS_P<3> BI 125 DDR0_DQSP5 V3 MEM_A_DQS_P<0> BI 125 DDR1_DQSP4 AA9 MEM_B_DQS_P<4> BI 125 26 23 22 IN MEM_A_ALERT_L AU5 DDR0_ALERT* DDR0_DQSP6 R3 MEM_A_DQS_P<1> BI 125 DDR1_DQSP5 V9 MEM_B_DQS_P<7> BI 125 21 OUT CPU_DIMM_VREFCA BN13 DDR_VREF_CA DDR0_DQSP7 M3 MEM_A_DQS_P<2> BI 125 26 25 24 OUT MEM_B_PAR AJ7 DDR1_PAR DDR1_DQSP6 P9 MEM_B_DQS_P<6> BI 125 DDR1_DQSP7 L9 MEM_B_DQS_P<5> BI 125 DDR0_DQSP8 AY3 NC 26 23 22 OUT MEM_A_ACT_L AU3 DDR0_ACT* 26 25 24 IN MEM_B_ALERT_L AR8 DDR1_ALERT* DDR1_DQSP8 AW9 NC 26 25 24 OUT MEM_B_ACT_L AT9 DDR1_ACT* RSVD BK28 NC NC BP13 DDR0_VREF_DQ RSVD AJ8 NC BR13 DDR1_VREF_DQ RSVD B30 NC 21 OUT CPU_DIMMB_VREFDQ RSVD BH30 NC 26 23 22 OUT MEM_A_A<0> AH3 DDR0_MA0 DDR0_BA0 AH5 MEM_A_BA<0> OUT 22 23 26 RSVD BJ28 NC AP4 DDR0_MA1 DDR0_BA1 AH1 MEM_A_BA<1> OUT 22 23 26 26 23 22 OUT MEM_A_A<1> AN4 DDR0_MA2 DDR0_BG0 AU1 MEM_A_BG<0> OUT 22 23 26 26 25 24 OUT MEM_B_A<0> AJ9 DDR1_MA0 DDR1_BA0 AH8 MEM_B_BA<0> OUT 24 25 26 AP5 DDR0_MA3 DDR0_BG1 AU2 MEM_A_BG<1> OUT 22 23 26 26 25 24 OUT MEM_B_A<1> AK6 DDR1_MA1 DDR1_BA1 AH9 MEM_B_BA<1> OUT 24 25 26 26 23 22 OUT MEM_A_A<2> AP2 DDR0_MA4 26 25 24 OUT MEM_B_A<2> AK5 DDR1_MA2 DDR1_BG0 AR9 MEM_B_BG<0> OUT 24 25 26 AP1 DDR0_MA5 26 25 24 OUT MEM_B_A<3> AL5 DDR1_MA3 DDR1_BG1 AR7 MEM_B_BG<1> OUT 24 25 26 26 23 22 OUT MEM_A_A<3> AP3 DDR0_MA6 26 25 24 OUT MEM_B_A<4> AL6 DDR1_MA4 AN1 DDR0_MA7 26 25 24 OUT MEM_B_A<5> AM6 DDR1_MA5 26 23 22 OUT MEM_A_A<4> AN3 DDR0_MA8 26 25 24 OUT MEM_B_A<6> AN7 DDR1_MA6 AT4 DDR0_MA9 26 25 24 OUT MEM_B_A<7> AN10 DDR1_MA7 26 23 22 OUT MEM_A_A<5> AH2 DDR0_MA10 26 25 24 OUT MEM_B_A<8> AN8 DDR1_MA8 AN2 DDR0_MA11 26 25 24 OUT MEM_B_A<9> AR11 DDR1_MA9 26 23 22 OUT MEM_A_A<6> AU4 DDR0_MA12 26 25 24 OUT MEM_B_A<10> AH7 DDR1_MA10 AE3 DDR0_MA13 26 25 24 OUT MEM_B_A<11> AN11 DDR1_MA11 A 26 23 22 OUT MEM_A_A<7> AG4 DDR0_MA14 26 25 24 OUT MEM_B_A<12> AR10 DDR1_MA12 SYNC_MASTER=j380_mlb SYNC_DATE=02/09/2017 A 26 23 22 OUT MEM_A_A<8> AD1 DDR0_MA15 26 25 24 OUT MEM_B_A<13> AF9 DDR1_MA13 AH4 DDR0_MA16 26 25 24 OUT MEM_B_A<14> AH11 DDR1_MA14 PAGE TITLE 26 23 22 OUT MEM_A_A<9> 26 25 24 OUT MEM_B_A<15> AF8 DDR1_MA15 26 25 24 OUT MEM_B_A<16> AH10 DDR1_MA16 CPU DDR4 Interfaces 26 23 22 OUT MEM_A_A<10> 26 23 22 OUT MEM_A_A<11> DRAWING NUMBER SIZE 26 23 22 OUT MEM_A_A<12> Apple Inc. 051-02888 D 26 23 22 OUT MEM_A_A<13> NOTICE OF PROPRIETARY PROPERTY: REVISION 26 23 22 OUT MEM_A_A<14> THE INFORMATION CONTAINED HEREIN IS THE 1.0.0 PROPRIETARY PROPERTY OF APPLE INC. 26 23 22 OUT MEM_A_A<15> THE POSESSOR AGREES TO THE FOLLOWING: BRANCH I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 26 23 22 OUT MEM_A_A<16> II NOT TO REPRODUCE OR COPY IT EVT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED PAGE 7 OF 200 BOM_COST_GROUP=CPU & CHIPSET SHEET 3 7 OF 131 8 7 6 5 4 2 1 8 7 6 5 4 3 2 1 PPVCC_S0_CPU 6 8 58 115 8 PPVCCGT_S0_CPU 115 58 PPVCCIO_S0_CPU NC BL31 RSVD U0500 VCC AB32 BL34 RSVD 5 8 10 115 AP14 RSVD CFL-H-BDGADR4-IL VCC AB35 AP29 RSVD NC 45W NC SYM 5 OF 13 VCC AB36 AT14 VCCGT U0500 VCCGT BE34 AT31 VCCGT VCCGT BE35 NC CRITICAL VCC AB37 AT32 VCCGT CFL-H-BDGADR4-IL VCCGT BE36 AT33 VCCGT VCCGT BE37 115 58 8 6 PPVCC_S0_CPU AP38 VCC U0500 VCCIO AG12 115 PP1V2_S3_CPUDDR OMIT_TABLE VCC AB38 AT34 VCCGT 45W VCCGT BE38 AP37 VCC BGA VCCIO G15 AT35 VCCGT VCCGT BF13 AP36 VCC VCCIO G17 AA6 VDDQ VCC AC13 AT36 VCCGT SYM 7 OF 13 VCCGT BF14 AP35 VCC SYM 6 OF 13 VCCIO G19 AE12 VDDQ AT37 VCCGT POWER VCCGT BF29 POWER VDDQ VCC AC14 AT38 VCCGT VCCGT BF30 AF5 VDDQ AU14 VCCGT CRITICAL VCCGT BF31 AF6 VDDQ VCC AC29 AU29 VCCGT VCCGT BF32 AG5 VDDQ AU30 VCCGT OMIT_TABLE VCCGT BF35 AP32 VCC 45W VCCIO G21 AG9 VDDQ VCC AC30 AU31 VCCGT VCCGT BF36 AP31 VCC VCCIO H15 AJ12 VDDQ AU32 VCCGT VCCGT BF37 CFL-H-DDR4-IL AL11 VDDQ VCC AC31 AU35 VCCGT VCCGT BF38 AP6 VDDQ AU36 VCCGT VCCGT BG29 AP30 VCC CRITICAL VCCIO H16 AP7 VDDQ VCC AC32 AU37 VCCGT VCCGT BG30 OMIT_TABLE AR12 VDDQ AU38 VCCGT VCCGT BG31 AP13 VCC VCCIO H17 AR6 VDDQ VCC AC33 AV29 VCCGT VCCGT BG32 D D AN38 VCC VCCIO H19 AT12 VDDQ AV30 VCCGT VCCGT BG33 AW6 VDDQ VCC AC34 AV31 VCCGT VCCGT BG34 C AY6 VDDQ AV32 VCCGT VCCGT BG35 AN37 VCC VCCIO H20 VDDQ VCC AC35 AV33 VCCGT VCCGT BG36 B J5 VDDQ AV34 VCCGT VCCGT BH33 AN36 VCC VCCIO H21 J6 VDDQ VCC AC36 AV35 VCCGT VCCGT BH34 OUT 8 69 K12 VDDQ AV36 VCCGT VCCGT BH35 OUT 9 69 AN35 VCC VCCIO H26 K6 VDDQ VCC AD13 AW14 VCCGT VCCGT BH36 L12 VDDQ AW31 VCCGT VCCGT BH37 AN34 VCC VCCIO H27 L6 VDDQ VCC AD14 AW32 VCCGT VCCGT BH38 R6 VDDQ AW33 VCCGT VCCGT BJ16 AN33 VCC VCCIO J15 T6 VDDQ VCC AD31 AW34 VCCGT VCCGT BJ17 W6 AW35 VCCGT VCCGT BJ19 AN32 VCC VCCIO J16 Y12 VCC AD32 AW36 VCCGT VCCGT BJ20 AW37 VCCGT VCCGT BJ21 AN31 VCC VCCIO J17 VCC AD33 AW38 VCCGT VCCGT BJ23 AY29 VCCGT VCCGT BJ24 AN14 VCC VCCIO J19 VCC AD34 AY30 VCCGT VCCGT BJ26 AY31 VCCGT VCCGT BJ27 AN13 VCC VCCIO J20 VCC AD35 AY32 VCCGT VCCGT BJ37 AY35 VCCGT VCCGT BJ38 AM36 VCC VCCIO J21 VCC AD36 AY36 VCCGT VCCGT BK16 AY37 VCCGT VCCGT BK17 AM35 VCC VCCIO J26 VCC AD37 AY38 VCCGT VCCGT BK19 BA13 VCCGT VCCGT BK20 AM34 VCC VCCIO J27 VCC AD38 BA14 VCCGT VCCGT BK21 BA29 VCCGT VCCGT BK23 AM33 VCC VCC AE13 BA30 VCCGT VCCGT BK24 BA31 VCCGT VCCGT BK26 AM32 VCC VCCIO_SENSE H14 CPU_VCCIOSENSE_P VCC AE14 BA32 VCCGT VCCGT BK27 AM31 VCC VSSIO_SENSE J14 CPU_VCCIOSENSE_N BA33 VCCGT VCCGT BL15 AM30 VCC OUT 8 78 VCC AE30 BA34 VCCGT VCCGT BL16 OUT 9 78 BA35 VCCGT VCCGT BL17 VCC AE31 BA36 VCCGT VCCGT BL23 BB13 VCCGT VCCGT BL24 AM29 VCC VCCSA J30 PPVCC
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